Publications

Copyright note: All the papers below have been copyrighted to the IEEE or the ACM. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE or the ACM.

Papers in Peer-Reviewed Journals

Note: Student names are marked (*).

H. El-Razouk* and A. Reyhani-Masoleh , “New Architectures for Digit-Level Single, Hybrid-Double, Hybrid-Triple Field Multiplications and Exponentiation Using Gaussian Normal Bases,” IEEE Transactions on Computers, 65(8): 2495-2509(2016).

Ebrahim H. Abdurahman* and A. Reyhani-Masoleh, “High-Speed Hybrid-Double Multiplication Architectures Using New Serial-Out Bit-Level Mastrovito Multipliers,” IEEE Transactions on Computers, 65(6): 1734-1747 (2016).

D. Gangopadhyay* and A. Reyhani-Masoleh, “Multiple-bit Parity-based Concurrent Fault Detection Architecture for Parallel CRC Computation,” IEEE Transactions on Computers, 65(7): 2143-2157 (2016).

A. Reyhani-Masoleh, “Comments on “Low-Latency Digit-Serial Systolic Double Basis Multiplier over GF(2^m) Using Subquadratic Toeplitz Matrix-Vector Product Approach,” IEEE Transactions on Computers, 64(4): 1215-1216 (2015).

R. Azarderakhsh* and A. Reyhani-Masoleh, “Parallel and High-Speed Computations of Elliptic Curve Cryptography Using Hybrid-Double Multipliers," IEEE Transactions on Parallel and Distributed Systems, 26(6): 1668-1677 (2015).

Hayssam El-Razouk*, Arash Reyhani-Masoleh, and Guang Gong, “New Hardware Implementations of WG(29,11) and WG-16 Stream Ciphers Using Polynomial Basis,” IEEE Transactions on Computers, 64(7): 2020-2035 (2015).

Ebrahim H. Abdurahman* and Arash Reyhani-Masoleh, “New Regular Radix-8 Scheme for Elliptic Curve Scalar Multiplication Without Pre-computation”, IEEE Transactions on Computers, 64(2): 438-451 (2015).

S. Bayat-Sarmadi, M. Mozaffari-Kermani*, and A. Reyhani-Masoleh, “Efficient and Concurrent Reliable Realization of the Secure Cryptographic SHA-3 Algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(7): 1105-1109 (2014).

Hayssam El-Razouk*, Arash Reyhani-Masoleh, and Guang Gong, “New Implementations of the WG Stream Cipher,” IEEE Transactions on VLSI Systems, 22(9): 1865-1878 (2014).

R. Azarderakhsh* and A. Reyhani-Masoleh, “High-Performance Implementation of Point Multiplication on Koblitz Curves”, IEEE Transactions on Circuits and Systems (TCAS) part II, Systems 60-II(1): 41-45 (2013).

R. Azarderakhsh* and A. Reyhani-Masoleh, "Low Complexity Multiplier Architectures for Single and Hybrid-Double Multiplications in Gaussian Normal Bases", IEEE Transactions on Computers, 62(4): 744-757 (2013).

M. Mozaffari-Kermani* and A. Reyhani-Masoleh, Efficient and High-Performance Parallel Hardware Architectures for the AES-GCM, " IEEE Transactions on Computers, 68(8): 1165-1178 (2012).

R. Azarderakhsh* and A. Reyhani-Masoleh, "Efficient FPGA Implementations of Point Multiplication on Binary Edwards and Generalized Hessian Curves Using Gaussian Normal Basis,” IEEE Transactions on VLSI Systems, 20(8): 1453-1466 (2012).

Mohsen Bahramali*, Jin Jiang, Arash Reyhani-Masoleh: A Fault Detection Scheme for the FPGA Implementation of SHA-1 and SHA-512 Round Computations. J. Electronic Testing 27(4): 517-530 (2011).

R. Azarderakhsh* and A. Reyhani-Masoleh, "Secure Clustering and Symmetric Key Establishments in Heterogeneous Wireless Sensor Networks", EURASIP Journal on Wireless Communication and Networking (JWCN), Special Issue on Security and Resiliency for Smart Devices and Applications, 12 pages, Volume 2011 (2011).

A. Hariri* and A. Reyhani-Masoleh, “Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields,” IEEE Transactions on VLSI Systems, 19(11): 2125-2129, Nov. 2011.

M. Mozaffari-Kermani* and A. Reyhani-Masoleh, “A Low-Power High-Performance Concurrent Fault Detection Approach for the Composite Field S-box and Inverse S-box,” IEEE Transactions on Computers, Special Issue on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems, 60(9): 1327-1340, Sep. 2011.

A. Hariri* and A. Reyhani-Masoleh, “Concurrent Error Detection in Montgomery Multiplication over Binary Extension Fields," IEEE Transactions on Computers, Special Issue on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems, 60(9): 1341-1353, Sep. 2011.

M. Mozaffari-Kermani* and A. Reyhani-Masoleh, “A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields,” IEEE Transactions on VLSI Systems, Vol. 19, No. 1, 85-91, Jan. 2011.

M. Mozaffari-Kermani* and A. Reyhani-Masoleh, “Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard,” IEEE Transactions on Computers, Special Issue on System Level Design of Reliable Architectures, pp. 608-622, Vol. 59, No. 5, May 2010.

M. Mozaffari-Kermani* and A. Reyhani-Masoleh, “Fault Detection Structures of S-boxes and Inverse S-boxes for the Advanced Encryption Standard,” Journal of Electronic Testing Theory and Applications, Vol. 25, No. 4-5, pp. 225-245, 2009.

A. Hariri* and A. Reyhani-Masoleh, “Bit-Serial and Bit-Parallel Montgomery Multiplication and Squaring over GF(2^m),” IEEE Transactions on Computers, pp. 1332-1345, Vol. 58, No. 10, October 2009.

A. Reyhani-Masoleh and M. A. Hasan, "Fault Detection Architectures for Field Multiplication Using Polynomial Bases," IEEE Transactions on Computers, Special Section on Fault Diagnosis and Tolerance in Cryptography, pp 1089-1103, Vol. 55, No. 9, September 2006.

A. Reyhani-Masoleh, "Efficient Algorithms and Architectures for Field Multiplication Using Gaussian Normal Bases," IEEE Transactions on Computers, pp. 34-47, Vol. 55, No. 1, January 2006.
A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Word-Level Sequential Normal Basis Multipliers," IEEE Transactions on Computers, pp. 98-110, Vol. 54, No. 2, February 2005.
A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Bit Parallel Polynomial Basis Multiplication over GF(2^m)," IEEE Transactions on Computers, pp. 945-959, Vol. 53, No. 8, August 2004.
A. Reyhani-Masoleh and M. A. Hasan, "Efficient Digit-Serial Normal Basis Multipliers over Binary Extension Fields," ACM Transactions on Embedded Computing Systems (TECS), Special Issue on Embedded Systems and Security, pp. 575-592, Volume 3, Issue 3, August 2004.
A. Reyhani-Masoleh and M. A. Hasan, "Towards Fault Tolerant Cryptographic Computations over Finite Fields," ACM Transactions on Embedded Computing Systems (TECS), Special Issue on Embedded Systems and Security, pp. 593 - 613, Volume 3 , Issue 3, August 2004.
A. Reyhani-Masoleh and M. A. Hasan, "Fast Normal Basis Multiplication Using General Purpose Processors," IEEE Transactions on Computers, pp. 1379-1390, Vol. 52, No. 11, November 2003.
A. Reyhani-Masoleh and M. A. Hasan, "Efficient Multiplication Beyond Optimal Normal Bases," IEEE Transactions on Computers, Special Issue on Cryptographic Hardware and Embedded Systems, pp. 428-439 Vol. 52, No. 4, April 2003 (acceptance ratio: ≈15%).
A. Reyhani-Masoleh and M. A. Hasan, "A New Construction of Massey-Omura Parallel Multiplier over GF(2^m)," IEEE Transactions on Computers, pp. 511-520, Vol. 51, No. 5, May 2002.

Papers in Refereed Conference/Workshop Proceedings and Book Chapters

Mostafa M. I. Taha, Arash Reyhani-Masoleh and Patrick Schaumont, "Keymill: Side-Channel Resilient Key Generator,'' a chapter in proceedings of Selected Areas in Cryptography, SAC 2016, 14 pages (double-blinded reviewed).

Amir Kouzeh Geran* and Arash Reyhani-Masoleh, “A CRC-Based Concurrent Fault Detection Architecture for Galois/Counter Mode (GCM),” in proceedings of the 23rd IEEE Symposium on Computer Arithmetic, ARITH 2016: 24-31 (double-blinded reviewed).

Hayssam El-Razouk* and Arash Reyhani-Masoleh, “New Bit-Level Serial GF (2^m) Multiplication Using Polynomial Basis,” in proceedings of the 22nd IEEE Symposium on Computer Arithmetic, ARITH 2015: 129-136 (double-blinded reviewed, acceptance rate: 42%).

A. Hariri* and A. Reyhani-Masoleh, “On Countermeasures Against Fault Attacks on Elliptic Curve Cryptography Using Fault Detection,” Chapter 12 of the book “Fault Analysis in Cryptography,” Editors: Marc Joye and Michael Tunstall, pp. 157-169, Springer, 2012.

M. Mozaffari Kermani* and A. Reyhani-Masoleh, “Reliable Hardware Architectures for the Third-Round SHA-3 Finalist Grostl Benchmarked on FPGA Platform,” in proceedings of the 26st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems, pp. 325-331, Oct. 2011.

M. Mozaffari Kermani* and A. Reyhani-Masoleh, “A High-Performance Fault Diagnosis Approach for the AES SubBytes utilizing Mixed Bases,” in proceedings of Fault Diagnosis and Tolerance in Cryptography (FDTC 2011), pp 80-87, Sep. 2011.

R. Azarderakhsh* and A. Reyhani-Masoleh, “A Modified Low Complexity Digit-Level Gaussian Normal Basis Multiplier,” a chapter in proceedings of 3rd International Workshop on the Arithmetic of Finite Fields (WAIFI 2010), LNCS No. 6087, pages 25-40, June 2010 (acceptance rate: 45%).
M. Mozaffari Kermani* and A. Reyhani-Masoleh, “A Low-Cost S-boxes for the Advanced Encryption Standard Using Normal Basis,” in proceedings of IEEE International Conference on Electro/Information Technology, EIT-2009, pages 52-55, June 2009 (invited paper).
C. Kennedy* and A. Reyhani-Masoleh, “High-Speed CRC Computation Using Improved State-Space Transformations,” in proceedings of IEEE International Conference on Electro/Information Technology, EIT-2009, pages 9-14, June 2009.
M. Bahramali*, J. Jiang, and A Reyhani Masoleh, "Security Issues in Industrial Control Systems," NPIC-HMIT 2009 - Nuclear Plant Instrumentation, Control, and Human-Machine Interface Technologies, 10 pages, April 5-9, 2009.

R. Azarderakhsh*, A. Reyhani-Masoleh, and Z. Abid, “A Key Management Scheme for Cluster Based Wireless Sensor Networks,” in proceedings of IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Volume 2, 17-20 Dec. 2008, Pages: 222 - 227 (acceptance rate: 40%).
X. Yuan, H. Jürgensen, R. Azarderakhsh*, and A. Reyhani-Masoleh, “Key Management for Wireless Sensor Networks Using Trusted Neighbours,” in proceedings of IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, 2008, EUC '08, Volume 2, 17-20 Dec. 2008, Pages: 228 - 233 (acceptance rate: 40%).
C. Kennedy* and A. Reyhani-Masoleh, “High-Speed Parallel CRC Circuits,” in proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers 2008, pages 1823-1829, October 2008.
M. Mozaffari Kermani* and A. Reyhani-Masoleh, “A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis,” a chapter in proceedings of Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008), Lecture Notes in Computer Science (LNCS) No.5154: 113-129 (acceptance rate: 25%).
A. Reyhani-Masoleh, “A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases,” a chapter in proceedings of Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008), LNCS No.5154: 300-314 (acceptance rate: 25%).
A. Hariri* and A. Reyhani-Masoleh, “Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields,” a chapter in proceedings of 2nd International Workshop on the Arithmetic of Finite Fields (WAIFI 2008), LNCS No. 5130: 103-116, July 2008 (acceptance rate: 47%)
A. Hariri* and A. Reyhani-Masoleh, “Fault Detection Structures for the Montgomery Multiplication over Binary Extension Fields,” in proceedings of Fault Diagnosis and Tolerance in Cryptography (FDTC 2007), pp 37 -43, Sept. 2007.
M. Mozaffari-Kermani* and A. Reyhani-Masoleh, “A Structure-independent Approach for Fault Detection Hardware Implementations of the Advanced Encryption Standard,” in proceedings of FDTC 2007, pp 47 -53, Sept. 2007.
M. Mozaffari Kermani* and A. Reyhani-Masoleh, “Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard,” in proceedings of the 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06) pp 572-580, Oct. 2006.
M. Mozaffari Kermani* and A. Reyhani-Masoleh, “Parity Prediction of S-Box for AES,” in proceedings of Canadian Conference on Electrical and Computer Engineering (IEEE CCECE 2006), pp 2357-2360, May 2006.

A. Reyhani-Masoleh and M. A. Hasan, "On Low Complexity Bit Parallel Polynomial Basis Multipliers," a chapter in proceedings of Cryptographic Hardware and Embedded Systems (CHES 2003), LNCS No. 2779, pp 189-202, Sep. 2003 (acceptance rate: 29%).
A. Reyhani-Masoleh and M. A. Hasan, "Low Complexity Sequential Normal Basis Multipliers over GF(2m)," in proceedings of the 16th IEEE Symposium on Computer Arithmetic, pp 188-195, June 2003 (acceptance rate: 34%).
A. Reyhani-Masoleh and M. A. Hasan, "Error Detection in Polynomial Basis Multipliers over Binary Extension Fields," a chapter in proceedings of Cryptographic Hardware and Embedded Systems (CHES 2002), LNCS No. 2523, pp 515-528, Aug. 2002 (acceptance rate: 39%).
A. Reyhani-Masoleh and M. A. Hasan, "Efficient Digit-Serial Normal Basis Multipliers over GF(2m),'' in proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2002), pp 781-784, May 2002.
A. Reyhani-Masoleh and M. A. Hasan, "Fast Normal Basis Multiplication Using General Purpose Processors,'' a chapter in proceedings of Selected Areas in Cryptography (SAC 2001), LNCS No. 2259, pp. 247-261, Aug. 2001 (acceptance rate: 44%).
A. Reyhani-Masoleh and M. A. Hasan, "On Efficient Normal Basis Multiplication," a chapter in proceedings of Indocrypt 2000, LNCS No. 1977, pp. 213-224, December 2000 (acceptance rate: 45%).
A. Reyhani-Masoleh and M. A. Hasan, "A Reduced Redundancy Massey-Omura Parallel Multiplier over GF(2m)," in proceedings of the 20th Biennial Symposium on Communications, pp. 308-312, May 2000.
A. Reyhani-Masoleh and M. A. Hasan, "A New Efficient Architecture of Mastrovito Multiplier over GF(2m)," in proceedings of the 20th Biennial Symposium on Communications, pp. 59-63, May 2000.

Presentations at Professional Meetings/Workshops/Invited Talks

“New Bit-Level Serial GF (2^m) Multiplication Using Polynomial Basis,” the 22nd IEEE Symposium on Computer Arithmetic, ARITH 2015, Lyon, France, June 24, 2015.
“Hardware Designs using Normal Basis”, ComSec Group Seminar, Communications Security (ComSec) lab, University of Waterloo, Waterloo, Ontario, April 12, 2012.
“A Modified Low Complexity Digit-Level Gaussian Normal Basis Multiplier,” 3^rd International Workshop on the Arithmetic of Finite Fields (WAIFI 2010), Istanbul, Turkey, June 28 2010.
“A New Bit-Serial Architecture for Field Multiplication Using Polynomial Bases,” International Workshop on Cryptographic Hardware and Embedded Systems (CHES 08), Washington DC, USA, August 13, 2008.
“A Lightweight Concurrent Fault Detection Scheme for the AES S-Boxes Using Normal Basis,” ,” International Workshop on Cryptographic Hardware and Embedded Systems (CHES 08), Washington DC, USA, August 11, 2008.
“Digit-Serial Structures for the Shifted Polynomial Basis Multiplication over Binary Extension Fields,” International Workshop on the Arithmetic of Finite Fields (WAIFI 08), Siena, Italy, July 8, 2008.
“High Performance Computations for Cryptography and Error Control Coding,” Research in Motion, Waterloo, Ontario, Canada, Feb. 26, 2008.
Represent the ECE department at the Ontario Engineering Graduate Studies Fair (OEGSF) University of Waterloo, Sep. 22, 2007.
"Parity-based Fault Detection Architecture of S-box for Advanced Encryption Standard", IEEE International Symposium on Defectand Fault Tolerance in VLSI Systems (DFT 06), Arlington/Washington DC, USA, Oct. 6, 2006.
“On Low Complexity Bit Parallel Polynomial Basis Multipliers," International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003), Cologne, Germany, Sep. 9, 2003
"Error Detection in Polynomial Basis Multipliers over Binary Extension Fields," International Workshop on Cryptographic Hardware and Embedded Systems (CHES 2002), San Francisco Bay (Redwood City), USA, Aug. 15, 2002.
"A Reduced Redundancy Massey-Omura Parallel Multiplier over GF(2^m)," the 20th Biennial Symposium on Communications, Kingston, Ontario, May 2000.
"A New Efficient Architecture of Mastrovito Multiplier over GF(2^m)," the 20th Biennial Symposium on Communications, Kingston, Ontario, May 2000.

Theses:

A. Reyhani-Masoleh, "Low Complexity and Fault Tolerant Arithmetic over Binary Extension Field," Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Waterloo, Ontario, Canada, 2001 (supervisor: Prof. M. A. Hasan).
A. Reyhani-Masoleh, "Piece-Wise Linear Modeling, Analysis, and Design of Nonlinear Circuits," M.Sc. Thesis, Department of Electrical and Computer Engineering, University of Tehran, Tehran, Iran, 1991 (supervisor: Prof. P. Jabedar-Maralani).
A. Reyhani-Masoleh, "Design and Implementation of a Telephone Central Switching System Using the Microprocessor Z80," B.Sc. Thesis, Department of Electrical Engineering, Iran University of Science and Technology, Tehran, Iran, 1989 (supervisor: Prof. A. Afkar).